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CYK001M16ZCCA MoBL3TM
16-Mbit (1M x 16) Pseudo Static RAM
Features
* Wide voltage range: 2.70V-3.30V * Access Time: 55 ns, 70 ns * Ultra-low active power -- Typical active current: 3 mA @ f = 1 MHz -- Typical active current: 13 mA @ f = fmax * Ultra low standby power * Automatic power-down when deselected * CMOS for optimum speed/power * Deep Sleep Mode * Offered in a 48-ball BGA Package (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by asserting Chip Enable (CE) and Output Enable (OE) inputs LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes. This device incorporates a Low Power mode wherein data integrity is not guaranteed, but Power Consumption reduces to less than 100 W. This mode (Deep Sleep Mode) is enabled by driving ZZ LOW.See the Truth Table for a complete description of Read, Write, and Deep Sleep mode.
Functional Description
The CYK001M16ZCCAU is a high-performance CMOS Pseudo static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DATA IN DRIVERS
ROW DECODER
1M x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE OE BLE
A11 A12 A13 A14 A15 A16 A17 A18 A19
CE
Power-Down Circuit
ZZ
BHE BLE
CE
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05454 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised May 15, 2004
CYK001M16ZCCA MoBL3TM
Pin Configuration[2, 3, 4]
FBGA
Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15
A18
2 OE BHE I/O10 I/O11
3 A0 A3 A5 A17
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6 ZZ I/O0 I/O2 Vcc Vss I/O6 I/O7
NC
A B C D E F G H
I/O12 GND I/O13 A19 A8 A14 A12 A9
Product Portfolio[5]
Power Dissipation Product Min. CYK001M16ZCCAU 2.70 VCC Range (V) Typ.[5] 3.0 Max. 3.30 55 70 Speed (ns) Operating ICC(mA) f = 1MHz Typ.[5] 3 Max. 5 f = fmax Typ.[5] 13 Max. 22 17 Standby ISB2(A) Typ.[5] 80 Max. 150
Notes: 2. DNU pins have to be left floating. 3. Ball H6 can be used to upgrade to 32M density. 4. NC "no connect"--not connected internally to the die. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential ................. -0.4V to 4.6V DC Voltage Applied to Outputs in High Z State[6, 7, 8] ........................................-0.4V to 3.7V DC Input Voltage[6, 7, 8] .....................................-0.4V to 3.7V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA
Operating Range
Device CYK001M16ZCCA Range Industrial Ambient Temperature -25C to +85C VCC 2.70V to 3.30V
DC Electrical Characteristics (Over the Operating Range)
CYK001M16ZCCAU55 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VIN < VCC GND < VOUT < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels IOH = --0.1 mA IOL = 0.1mA VCC= 2.7V to 3.3V 0.8 * VCC -0.4 -1 -1 13 3 Test Conditions Min. 2.7 VCC - 0.4 0.4 VCC + 0.4V 0.4 +1 +1 22 5 0.8 * VCC -0.4 -1 -1 13 3 Typ.[5] 3.0 Max. 3.3 CYK001M16ZCCAU70 Min. 2.7 VCC - 0.4 0.4 VCC + 0.4V 0.4 +1 +1 17 5 Typ.[5] Max. 3.3 Unit V V V V V A A mA mA
ISB1
Automatic CE Power-Down Current -- CMOS Inputs
VCC = 3.3V CE > VCC-0.2V VIN > VCC-0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.30V CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V VCC = VCCMAX; ZZ = LOW VCC = 3.3V
100
525
100
525
A
ISB2
Automatic CE Power-Down Current -- CMOS Inputs Deep Sleep Current
80
150
80
150
A
IZZ
50
50
A
Notes: 6. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 7. VIH(Max) = Vcc + 0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested.
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Capacitance[9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance[9]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. BGA 55 17 Unit C/W C/W
AC Test Loads and Waveforms
VCC OUTPUT R1 VCC GND 30 pF INCLUDING JIG AND SCOPE R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns Equivalent to:
THEVENIN EQUIVALENT RTH OUTPUT VTH Unit V
Parameters R1 R2 RTH
3.0V VCC 22000 22000 11000
VTH 1.50 Note: 9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]
55 ns[14] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK[14] Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[12] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to
[11, 13]
70 ns Min. 70 55 70 5 55 25 70 35 5 25 25 5 25 55 25 70 5 10 0 25 10 70 60 60 0 0 45 60 45 0 25 25 5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z CE LOW to Low
[11, 13]
Min. 55[14] 5
Max.
5 2
OE HIGH to High Z[11, 13] Z[11, 13] Z[11, 13] 5 CE HIGH to High
BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[11, 13] BLE/BHE HIGH to HIGH Address Skew 55 45 45 0 0 40 50 25 0 5 Z[11, 13]
Low-Z[11, 13]
Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS
tSK
tOHA
tAA DATA VALID
DATA OUT
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)[14, 16]
ADDRESS
CE
tSK
tRC tHZCE
tACE
BHE/BLE
tLZBE
OE
tDBE
tHZBE tHZOE HIGH IMPEDANCE ICC ISB
DATA OUT VCC SUPPLY CURRENT
tLZOE HIGH IMPEDANCE tLZCE
tDOE DATA VALID
50%
50%
Notes: 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for Read Cycle.
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 17, 18, 19]
t WC ADDRESS tSCE
CE
tSA
WE
tAW
tPWE
tHA
BHE/BLE
tBW
OE
tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Write Cycle 2 (CE Controlled)[12, 13, 17, 18, 19]
t WC ADDRESS tSCE CE
tSA
tAW
tHA tPWE
WE tBW
BHE/BLE
OE t HZOE DATA I/O
DON'T CARE
tSD VALID DATA
tHD
Notes: 17. Data I/O is high impedance if OE > VIH. 18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE
CE
BHE/BLE
tBW tAW tHA
tSA
WE
tPWE
tSD DATAI/O
DON'T CARE
tHD tLZWE
VALID DATA tHZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18, 19] tWC ADDRESS
CE tSCE tAW BHE/BLE tSA WE tBW tHA
tPWE tSD tHD
DATA I/O
DON'T CARE
VALID DATA
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Deep Sleep Mode
This mode can be used to lower the power consumption of the PSRAM in an application. In this mode, the data integrity of the PSRAM is not guaranteed. Deep Sleep Mode can be enabled by driving ZZ LOW. The device stays in the deep sleep mode until ZZ is driven HIGH.
Deep Sleep Mode--Entry/Exit[20]
ZZ
Deep Sleep Mode
tCDR
CE or BLE / BHE
tR
Deep Sleep Access Timings[21, 22]
Parameter tCDR tR Description Chip Deselect to ZZ LOW Operation Recovery Time Min. 0 200 Max. Unit ns s
Truth Table[23]
ZZ H H H H H H H H H H H L CE H X L L L L L L L L L H WE X X H H H H H H L L L X OE X X L L L H H H X X X X BHE X H L H L L H L L H L H BLE X H L L H L L H L L H H Inputs/Outputs High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z High Z Mode Deselect/Power-down Deselect/Power-down Read (Upper Byte and Lower Byte) Read (Lower Byte only) Read (Upper Byte only) Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Deep Power-down Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Deep Sleep (IZZ)
Notes: 20. OE and the data pins are in a "don't care" state while the device is in Deep Sleep Mode. 21. All other timing parameters are as shown in the switching characteristics section. 22. tR applies only in the Deep Sleep Mode. 23. H = Logic HIGH, L = Logic LOW, X = Don't Care.
Document #: 38-05454 Rev. *B
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CYK001M16ZCCA MoBL3TM
Ordering Information
Speed (ns) 55 70 Ordering Code CYK001M16ZCCAU-55BAI CYK001M16ZCCAU-70BAI Package Name BA48K BA48K Package Type 48-ball Fine Pitch BGA (6 mm x 8mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8mm x 1.2 mm) Operating Range Industrial Industrial
Package Diagram
48-Lead FBGA (6 x 8 x 1.2 mm) BA48K
BOTTOM VIEW
TOP VIEW
O0.05 M C O0.25 M C A B A1 CORNER 1 2 3 4 5 6 O0.300.05(48X)
A1 CORNER
6
5
4
3
2
1
A B D E F G H C
A B C D E F G H
8.000.10
8.000.10
5.25
0.75 2.625
A B 6.000.10
A
1.875 0.75 3.75
0.25 C
0.530.05
0.210.05
B
6.000.10
0.15 C
0.15(4X)
REFERENCE JEDEC MO-207
SEATING PLANE
51-85150-*B
1.20 MAX
0.36
C
51-85193-*A
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05454 Rev. *B
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
CYK001M16ZCCA MoBL3TM
Document History Page
Document Title: CYK001M16ZCCA MoBL3TM 16-Mbit (1M x 16) Pseudo Static RAM Document Number: 38-05454 REV. ** *A ECN NO. 132407 220121 Issue Date 01/27/04 See ECN Orig. of Change AWK REF Description of Change New Data Sheet Changed the datasheet from AdvanceInformation to Final Added 55-ns speed bin and address skew restriction for 55-ns speed bin. Changed Izz from 30 A to 50 A. Changed ball A6 from NC to ZZ Modified ordering code in "Ordering Information" table on page 10 Replaced package diagram Modified MAX limit on DC Input voltage in `Maximum Ratings' section
*B
230851
See ECN
AJU
Document #: 38-05454 Rev. *B
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